Copyright 2013 David Glasco
Austin, TX 78726
Publications
David Glasco, Ph.D.
Technologist
Conference/Journal Papers
Keckler, S.W.; Dally, W.J.; Khailany, B.; Garland, M.; Glasco, D., "GPUs and the Future of Parallel Computing," in IEEE Micro, Volume: 31, Issue: 5,
pages 7-17, 2011
Brock, B. C., Carpenter, G. D., Chiprout, E., Dean, M. E., De Backer, P. L., Elnozahy, E. N., Franke, H., Giampapa, M. E., Glasco, D. B., Peterson, J.
L., Rajamony, R., Ravindran, R., Rawson, F. L., Rockhold, R. L., and Rubio, J. "Experience with building a commodity Intel-based ccNUMA system," in
IBM Journal of Research and Development, pages 207-228,Volume 45, Number 2, 2001.
Brock, B. C., Carpenter, G. D., Chiprout, E., Elnozahy, E. N., Dean, M., Glasco, D. B., Peterson, J. L., Rajamony, R., Rawson, F. L., Rockhold, R. L. and
Zimmerman, A. "Windows NT in a CC-NUMA System," Proceedings of the 3rd USENIX Windows NT Symposium, Seattle, Washington, pages 61-72, July
1999.
Sunada, D., Glasco, D. B. and Flynn, M. J. "Multiprocessor Architecture Using an Audit Trail for Fault Tolerance," [PDF] In Proceedings of the
Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, pages 40-47, June 1999.
Sunada, D., Glasco, D. B. and Flynn, M. J. "ABSS v2.0: a SPARC Simulator," In Proceedings of the Eighth Workshop on Synthesis and System
Integration of Mixed Technologies, pages 143-149, October 1998.
Glasco, D. B., Delagi, B. A. and Flynn, M. J. "The Impact of Cache Coherence Protocols on Systems Using Fine-Grain Data Synchronization," In
Proceedings of the International Conference of Parallel Architectures and Compilation Techniques, pages 79-88, August 1994.
Glasco, D. B., Delagi, B. A. and Flynn, M. J. "Write Grouping for Update-Based Cache Coherence Protocols," In Proceedings of the Sixth IEEE
Symposium of Parallel and Distributed Processing, pages 334-341, October 1994.
Glasco, D. B., Delagi, B. A. and Flynn, M. J. "Update-Based Cache Coherence Protocols for Scalable Shared-Memory Multiprocessors," In Proceedings
of the Twenty-seventh Annual Hawaii International Conference of System Sciences, pages 534-545, January 1994.
Glasco, D. B. and Sargent, M., "Using IBM's Marvelous Keyboard," Byte Magazine, pages 402-415, May 1983.
Book Chapters
Contributed to chapter 8, "Shared Memory Multiprocessors" of Computer Architecture: Pipelined and Parallel Processor Design," Michael J. Flynn, Jones
and Bartlett Publishers, Boston, 1995.
Contributed to chapter 8, "Keyboard and Video Display" of The IBM Personal Computer from the Inside Out, Murry Sargent, III and Richard L. Shoemaker,
Addison-Wesley Publishing Company, 1984.
Technical Reports
Sunada, D., Glasco, D. B. and Flynn, M. J. "Novel Checkpointing Algorithm for Fault Tolerance on a Tightly-Coupled Multiprocessor," Technical Report
CSL-TR-99-776, Computer Systems Laboratory, Stanford University, January 1999.
Sunada, D., Glasco, D. B. and Flynn, M. J. "Hardware-Assisted Algorithms for Checkpoints," Technical Report CSL-TR-98-756, Computer Systems
Laboratory, Stanford University, June 1998.
Sunada, D., Glasco, D. B. and Flynn, M. J. "ABSS v2.0: a SPARC Simulator," Technical Report CSL-TR-98-755, Computer Systems Laboratory, Stanford
University, April 1998.
Sunada, D. Glasco, D. B. and Flynn, M. J. "Fault Tolerance: Methods of Rollback Recovery," Technical Report CSL-TR-97-718. Computer Systems
Laboratory, Stanford University, March 1997.
Glasco, D. B. "Analysis of Update-Based Cache Coherence Protocols for Scalable Shared-Memory Multiprocessors," Ph.D. Dissertation, Computer
Systems Laboratory, Stanford University, December 1994. Also appears as Technical Report CSL-TR-94-670, Computer Systems Laboratory, Stanford
University, June 1995.
Glasco, D. B., Delagi, B. A. and Flynn, M. J. "Write Grouping for Update-Based Cache Coherence Protocols," Technical Report CSL-TR-94-612, Computer
Systems Laboratory, Stanford University, March 1994.
Glasco, D. B., Delagi, B. A. and Flynn, M. J. "The Impact of Cache Coherence Protocols On Systems Using Fine-Grain Data Synchronization," Technical
Report CSL-TR-94-611, Computer Systems Laboratory, Stanford University, March 1994.
Glasco, D. B., Delagi, B. A. and Flynn, M. J. "Design and Validation of Update-Based Cache Coherence Protocols," Technical Report
CSL-TR-94-613, Computer Systems Laboratory, Stanford University, March 1994.
Glasco, D. B., Delagi, B. A. and Flynn, M. J. "Update-Based Cache Coherence Protocols for Scalable Shared-Memory Multiprocessors," Technical Report
CSL-TR-94-588, Computer Systems Laboratory, Stanford University, November 1993.
Rader, C. M., Allen, D. L., Glasco, D. B. and Woodward, C. E. "MUSE - A Systolic Array for Adaptive Nulling with 64 Degrees of Freedom, Using Givens
Transformations and Wafer Scale Integration," Technical Report 886, Lincoln Laboratory, Massachusetts Institute of Technology, May 1990.
Research Disclosures
Glasco, D. B., Bannister, J. P., Carpenter, G. D., Dean, M. E., Dickol, J. E., Iachetta, R. N., Parades, J. A. and Rosilier, A. C. "sNUMA Cache Coherence
Shared Memory Multiprocessor," IBM Research Disclosures, 1999.
Glasco, D. B. "Pipelined Directory Structure for CC-NUMA Systems," IBM Research Disclosures, 1999.
Glasco, D. B. "Distributed Pending Buffer for CC-NUMA Systems," IBM Research Disclosures, 1999.
Glasco, D. B. "Automatic Generation of Coherence Protocol Logic," IBM Research Disclosures, 1999.
Glasco, D. B. "Mirroring Data Modifications in a CC-NUMA System," IBM Research Disclosures, 1999.
Bannister, J. P., Carpenter, G. D., Dean, M. E., De Backer, P. L., Dickol, J. E., Glasco, D. B., Iachetta, R. N., Paredes, J. A. and Rockhold, R. L.
"Startup Methodology for a NUMA Machine," IBM Research Disclosures, December 1998.
Bannister, J. P., Carpenter, G. D., Dean, M. E. and Glasco, D. B. "Non-Blocking Distributed Bus Switch for Multicomputer Systems," IBM Research
Disclosures, August 1998.