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David Glasco, Ph.D.
Technologist
Technologist
Copyright 2013 David Glasco
Austin, TX 78726
Austin, TX 78726
NVIDIA Patents (22)
8,392,667 Deadlock avoidance by marking CPU traffic as special
8,359,454 Memory access techniques providing for override of page table attributes
8,352,709 Direct memory access techniques that include caching segmentation data
8,347,065 System and method for concurrently managing memory access requests
8,347,064 Memory access techniques in an aperture mapped memory space
8,327,071 Interprocessor direct cache writes
8,325,194 Mitigating main crossbar load using dedicated connections for certain traffic types
8,271,734 Method and system for converting data formats using a shared cache coupled between clients and an external memory
8,244,984 System and method for cleaning dirty data in an intermediate cache using a data class dependent eviction policy
8,234,478 Using a data cache array as a DRAM load/store buffer
8,234,458 System and method for maintaining cache coherency across a serial interface bus using a snoop request and complete message
8,185,602 Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
8,156,404 L2 ECC implementation
8,135,926 Cache-based control of atomic operations in conjunction with an external ALU block
8,131,931 Configurable cache occupancy policy
8,108,610 Cache-based control of atomic operations in conjunction with an external ALU block
8,099,650 L2 ECC implementation
8,065,465 Mitigating main crossbar load using dedicated connections for certain traffic types
8,060,700 System, method and frame buffer logic for evicting dirty data from a cache using counters and data types
7,859,541 Apparatus, system, and method for using page table entries in a graphics system to provide storage format information for address translation
7,769,979 Caching of page access parameters
7,382,377 Render to texture cull
8,392,667 Deadlock avoidance by marking CPU traffic as special
8,359,454 Memory access techniques providing for override of page table attributes
8,352,709 Direct memory access techniques that include caching segmentation data
8,347,065 System and method for concurrently managing memory access requests
8,347,064 Memory access techniques in an aperture mapped memory space
8,327,071 Interprocessor direct cache writes
8,325,194 Mitigating main crossbar load using dedicated connections for certain traffic types
8,271,734 Method and system for converting data formats using a shared cache coupled between clients and an external memory
8,244,984 System and method for cleaning dirty data in an intermediate cache using a data class dependent eviction policy
8,234,478 Using a data cache array as a DRAM load/store buffer
8,234,458 System and method for maintaining cache coherency across a serial interface bus using a snoop request and complete message
8,185,602 Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
8,156,404 L2 ECC implementation
8,135,926 Cache-based control of atomic operations in conjunction with an external ALU block
8,131,931 Configurable cache occupancy policy
8,108,610 Cache-based control of atomic operations in conjunction with an external ALU block
8,099,650 L2 ECC implementation
8,065,465 Mitigating main crossbar load using dedicated connections for certain traffic types
8,060,700 System, method and frame buffer logic for evicting dirty data from a cache using counters and data types
7,859,541 Apparatus, system, and method for using page table entries in a graphics system to provide storage format information for address translation
7,769,979 Caching of page access parameters
7,382,377 Render to texture cull